D-Type Flip-Flop Simulator
Visualise how a positive edge-triggered D-type flip-flop captures data on the rising clock edge. Includes a timing diagram and step history. Matches AQA A Level CS (7517) specification §4.6.5.6.
📖 Learn Step-by-StepA positive edge-triggered D-type flip-flop captures the value of D on the rising edge of the clock signal. Q takes D's value; Q̄ is always the inverse of Q.
Timing Diagram
Working
- Current state: D = 0, Q = 0, Q̄ = 1
- On a rising clock edge (0 → 1), Q adopts the value of D
- If clock fires now: Q will become 0, Q̄ will become 1
D-Type Flip-Flop Practice Questions
A D-type flip-flop has D=1 when a rising clock edge occurs. What value does Q output after this edge?
A D-type flip-flop currently has Q=1. If D is set to 0 but no clock edge occurs, what is the value of Q?
A D-type flip-flop has Q=0 and Q̄=1. D is set to 1 and a rising edge occurs. What is the new value of Q̄?
A sequence of D values [1, 0, 1, 1] is applied to a D-type flip-flop, with a rising clock edge after each value is set. Starting from Q=0, how many times does Q change value across the 4 edges?
A 4-bit shift register is built from 4 D-type flip-flops. If the serial input sequence is 1, 0, 1, 1 (one bit per clock cycle), what value is stored in the register after 4 clock pulses? Give the answer in decimal.
Quick reference — D-type flip-flop
What is a flip-flop?
A flip-flop is a 1-bit memory element. It stores a single bit and updates only on a clock signal, making it the building block of registers and counters.
Edge-triggered vs level-triggered
A positive edge-triggered D-type updates Q on the rising edge (0 → 1) of the clock only. Changes to D at other times are ignored.
Key outputs
- Q — takes the value of D on the rising edge.
- Q̄ — always the inverse of Q.
Uses
Registers (groups of flip-flops storing multi-bit values), shift registers (serial-to-parallel/parallel-to-serial), and counters.