CPU & FDE Cycle Simulator
Explore the Von Neumann architecture, the Fetch-Decode-Execute cycle, and trace through a real program step by step. OCR J277 §1.1.1.
📖 Learn CPU & FDE CycleVon Neumann Architecture
Click on components to highlight them. Instructions and data are stored in the same memory.
🧠 Key Registers
- PC (Program Counter) — holds address of next instruction
- MAR (Memory Address Register) — holds address being read/written
- MDR (Memory Data Register) — holds data being transferred
- ACC (Accumulator) — holds results of calculations
- CIR (Current Instruction Register) — holds instruction being decoded
🔌 Buses
- Address Bus — carries memory addresses (one-way: CPU → memory)
- Data Bus — carries data/instructions (two-way)
- Control Bus — carries control signals (read/write, clock, etc.)